1. Field of the Invention
The present invention relates to a logic circuit for detecting outstripping of events and glitches occurring in simulated devices and for appropriately processing outputs of those devices, in a hardware logic simulation accelerator, and a hardware logic simulation accelerator including the same.
2. Description of the Related Art
A hardware logic simulation accelerator or a simulation engine, as disclosed, for example, in U.S. Pat. No. 4,942,615, is widely used to reduce execution time of a logic simulator simulating logic circuits consisting of a large number of logic devices. Recently, as simulated logic circuits become larger, more complex, and faster, hardware logic simulation accelerators have been required to be able to handle more detailed propagation delay times of the logic devices without negatively influencing acceleration performance.
In Japanese Unexamined Patent Publication (Kokai) No. 4-3229, a hardware logic simulation accelerator comprising an evaluation gate buffer having three evaluation gate memories in order to separately handle logic devices having substantially zero delay time such as wired OR's or AND's in ECL (Emitter Coupled Logic) from general logic devices having definite propagation delay times, is described by the same inventor as the present application.
Also, in Japanese Unexamined Patent Publication (Kokai) No. 3-26974, a hardware logic simulation accelerator comprising an event scheduler for handling logic devices having various propagation delay times, is described by the same inventor as the present application. When an input condition that changes an output of a simulated logic device is applied to the device, i.e., when an event occurs in the device, the event is stored with propagation delay time of the device into an event list of the event scheduler, and the event scheduler dispatches the event from the event list after the propagation time has elapsed on a simulation time scale.
In the event scheduler described in Kokai No. 3-26974, events scheduled in the event list are successively dispatched as they mature. However, in actual logic devices, if two conditions that change the output in opposite directions are successively applied to the device at an interval shorter than propagation delay time of that device, the device does not exhibit simple behavior. For example, if propagation delay time of the condition applied second elapses prior to propagation delay time of the condition applied first, the output of the device does not appear to change. Therefore, in the logic simulator, if an event that has occurred later outstrips another event that has occurred earlier, i.e., if event-outstripping occurs in the event list, these events must be cancelled.
Alternatively, if the propagation delay time of the condition applied first elapses prior to the propagation delay time of the condition applied second, a glitch appears to occur in the output of the device. In this situation, two events are successively dispatched from the event list, and thus a pulse having a short duration appears in the output of the simulated device. If the output of the actual device is a data signal changing in synchronization with a clock signal, the glitch does not cause a problem because the output becomes stable before the next clock pulse is input to the following stage. In this case, it is preferable to cancel the two events in order to reduce the number of evaluation times of propagating events (inertia delay mode). If the output of the actual device is a clock signal or a reset signal or an ancestor thereof, the glitch or descendant thereof may cause a malfunction such as racing. In this case, it is necessary to warn of this condition by outputting an undefined state from the simulated device during the short pulse. Furthermore, if the output of the actual device is included in a feedback loop, the glitch may cause undesired oscillation. In this case, it is necessary to warn of the condition by holding the undefined state until a definite event occurs and that event matures.
In order to detect the occurrence of event-outstripping or a glitch to process the outputs as mentioned above, it may be necessary to search the contents of the event list to find events for the same device and to perform operations such as cancellation of events or alteration of the undefined state. In a software simulator, these operation can be easily realized. In a hardware accelerator, however, these operations require large scale of hardware and adversely affect the acceleration performance.